Advanced RTL Design Techniques

1. Clock gating will impact in reducing 1. clock network power 2. leakage power 3. static power  2. Effect of CG insertion may cause   1. setup time violation   2. hold time violation   3. both   3. Pick the correct latch combination within a CG element of posedge and negedge trigger flops   1. active low latch, active low latch   2. active low latch, active high latch   3. active high latch, active low latch  4. Can we directly use a signal from a different clock domain as enable to CG element   1. Yes   2. No  5. Gated clock generated by CG element is    1. synchronous with respect to the input clock   2. asynchronous with respect to the input clock

Rule of Seven: Human mind can hold up to seven objects in one time Applying this rule in Chip design: FSM state which crossed 7 (or up to 9) states can be changed to HFSM- Hierarchical FSM which helps designers and architects easy to think, review, debug In SoC, If we have more than 7 (or up to 9) blocks under one hierarchy which indicates the structure is getting more complex. So design partition needed to minimize complexity Psychologically mind looks for more opportunities when we feed it with minimal objects. So at one time, we need to see minimal design objects for efficient thinking & design. Reference: Simple Art of SoC Design

APB Change Points

Recovery and Removal Time .  These are timing checks for asynchronous signals similar to the setup and hold check Asynchronous reset also should satisfy these checks in design to avoid metastability For Asynchronous reset, the problem with metastability will arise only while de-assertion of reset. Since de-assertion of reset can also be asynchronous. Reset synchronizer is the best way to avoid metastability  In the above figure, even though rst_n has been connected to both the flops. How the second flop avoids metastability? The first flop input is tied to logic-1  For the worst case, consider the reset is removed closest to the active edge of the clock the first flop shows metastability since it has to react to two different values - for input logic-1 or for reset value logic-0 in the case of the second flop, the input and output of the flop is at logic level-0 while during reset removal, it avoids metastability since there is no logic level change ...

Memory map or Address map gives information regarding how much address locations that a processor can access. The memory map shown below is taken from the ARM principles of Memory map whitepaper. Figure 1 shows a memory map or an address map organization for a typical SoC. Figure 1: 32-bit memory map  Figure 2: Versatile version of the 32bit ARM CPU Memory map Address map consists of Boot ROM: This Boot ROM address region for ARM CPU 32bit to start from 0x0000_0000 or 0xFFFF_0000 ROM, RAM, SoC I/O: This address region is recommended to align with 64KB and consists of Internal ROM, SRAM, static memory, SoC peripheral registers  Mapped I/O and additional SoC I/O: Address region of mapped I/O like PCIe DRAM address space: The address space recommended for DRAM should be contiguous and needs to  be placed near the high address region  of the memory map   Reference: [1] Principles of ARM Memory Maps [White Paper] http://infocenter.arm.co...

Reasons for Metastability 1. A path which does not meet its timing 2. An asynchronous signal is connected to a flop in synchronous clock domains Figure 1: Metastability From Figure 1, the signals which change in the setup or hold window will result in the metastable condition at flop output. After the metastability settling time, the flop output q will reach the intended value. Consider many data input signals changing in the timing window of flops and assume A', B', C', D', E' be its corresponding flops metastability outputs. A', B' and C' will reach the correct intended value whereas D' and E' will reach a previous value. Seeing the same metastability in voltage perspective, it is a state in which the signal voltage level is not stable(ie neither at logic 0 or logic 1)  and is floating in between the two levels. So chances of getting partial ON state in CMOS is more and hence it draws maximum current from VDD to GND (Short Circuit Cu...

Does the design honour power budget? Who will be responsible to ensure the estimated power metric aligned with chip power budget target??  "It is responsibility of the engineer working in every stage of ASIC development to ensure the power estimated will be within power budget of that stage of the design and keep the chip competitive in market with other vendors". EDA vendors are having solution for a early RTL Power estimation. Some EDA tools in market are  1. Cadence - Joules RTL Power Soution 2. Mentor Graphics - PowerPro These above tools are pretty famous since their turn around time of report generation is very minimal when compared with formal EDA Physical design tools. Design engineer can make use of any one of the above tool to find RTL power after a new feature or old feature enhancement or large number of bug fixes or before RTL release. Power optimization impact is more in the top level abstraction of design than in the below stages of design. ...