Advanced RTL Design Techniques

First let us discuss the need for Asynchronous FIFO. We use Gray code for the same reason we need Async FIFO. To transfer a stream of multi bit signal(bus) from one clock domain to a different clock domain, designers cannot use typical Data Synchronizers. Different bus signals from different data synchronizers converge at different period of time, and this typical problem is called the Re-convergence issue in ASIC Design world. To solve the problem, Asynchronous FIFO was designed. Again in Asynchronous FIFO, pointers should be synchronized from native clock domain to the other clock domain. Pointers are multi bit which could lead to re convergence issue all over again. Luckily, we know that pointers are not random unlike data stream. Both Read and Write pointers are incremented by one (+1) w.r.t clock edge on read & write from FIFO. Given that, we should look for a code which changes minimally on increment by one (ideally only one bit change), Gray code was the solution. Employing ...

Recovery and Removal Time .  These are timing checks for asynchronous signals similar to the setup and hold check Asynchronous reset also should satisfy these checks in design to avoid metastability For Asynchronous reset, the problem with metastability will arise only while de-assertion of reset. Since de-assertion of reset can also be asynchronous. Reset synchronizer is the best way to avoid metastability  In the above figure, even though rst_n has been connected to both the flops. How the second flop avoids metastability? The first flop input is tied to logic-1  For the worst case, consider the reset is removed closest to the active edge of the clock the first flop shows metastability since it has to react to two different values - for input logic-1 or for reset value logic-0 in the case of the second flop, the input and output of the flop is at logic level-0 while during reset removal, it avoids metastability since there is no logic level change ...

Reasons for Metastability 1. A path which does not meet its timing 2. An asynchronous signal is connected to a flop in synchronous clock domains Figure 1: Metastability From Figure 1, the signals which change in the setup or hold window will result in the metastable condition at flop output. After the metastability settling time, the flop output q will reach the intended value. Consider many data input signals changing in the timing window of flops and assume A', B', C', D', E' be its corresponding flops metastability outputs. A', B' and C' will reach the correct intended value whereas D' and E' will reach a previous value. Seeing the same metastability in voltage perspective, it is a state in which the signal voltage level is not stable(ie neither at logic 0 or logic 1)  and is floating in between the two levels. So chances of getting partial ON state in CMOS is more and hence it draws maximum current from VDD to GND (Short Circuit Cu...