Converting a conventional FIFO into a valid ready based FIFO

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Basic Memory Mapping in SoC

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Memory map or Address map gives information regarding how much address locations that a processor can access. The memory map shown below is taken from the ARM principles of Memory map whitepaper. Figure 1 shows a memory map or an address map organization for a typical SoC. Figure 1: 32-bit memory map  Figure 2: Versatile version of the 32bit ARM CPU Memory map Address map consists of Boot ROM: This Boot ROM address region for ARM CPU 32bit to start from 0x0000_0000 or 0xFFFF_0000 ROM, RAM, SoC I/O: This address region is recommended to align with 64KB and consists of Internal ROM, SRAM, static memory, SoC peripheral registers  Mapped I/O and additional SoC I/O: Address region of mapped I/O like PCIe DRAM address space: The address space recommended for DRAM should be contiguous and needs to  be placed near the high address region  of the memory map   Reference: [1] Principles of ARM Memory Maps [White Paper] http://infocenter.arm.com/help/topic/com.arm.doc.den0
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Gray Code for Asynchronous FIFO pointer. Why?

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First let us discuss the need for Asynchronous FIFO. We use Gray code for the same reason we need Async FIFO. To transfer a stream of multi bit signal(bus) from one clock domain to a different clock domain, designers cannot use typical Data Synchronizers. Different bus signals from different data synchronizers converge at different period of time, and this typical problem is called the Re-convergence issue in ASIC Design world. To solve the problem, Asynchronous FIFO was designed. Again in Asynchronous FIFO, pointers should be synchronized from native clock domain to the other clock domain. Pointers are multi bit which could lead to re convergence issue all over again. Luckily, we know that pointers are not random unlike data stream. Both Read and Write pointers are incremented by one (+1) w.r.t clock edge on read & write from FIFO. Given that, we should look for a code which changes minimally on increment by one (ideally only one bit change), Gray code was the solution. Employing
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System Verilog Assertions for Power Gating Sequence

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LOW POWER DESIGN - SYSTEM VERILOG ASSERTIONS (SVA) Power Gating has become the most common strategy in today's trending nm technology. Power intent designs are dominating the chip, which needs more verification attention and different strategies to verify the intents. So, a generic SVA is arrived to verify the Power Shut Off (PSO) sequence. A major decision to make is choosing which design should adopt PSO. PSO is most favourable for a design which spends an accountable amount of time in idle period without doing any active operation. Energy saved from PSO should be more than the energy spent in performing PSO sequence (includes supportive Hardware mechanism). Power sequence control is done by a separate Power Controller management mechanism in hardware or can be controlled by software configuration. The sequence of operation in PSO is shown below. Power Shut Off Sequence The time relation between each sequence will depend on the bus frequency or the Powe
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