System Verilog Assertions for Power Gating Sequence

LOW POWER DESIGN - SYSTEM VERILOG ASSERTIONS (SVA)

Power Gating has become the most common strategy in today's trending nm technology. Power intent designs are dominating the chip, which needs more verification attention and different strategies to verify the intents. So, a generic SVA is arrived to verify the Power Shut Off (PSO) sequence.

A major decision to make is choosing which design should adopt PSO. PSO is most favourable for a design which spends an accountable amount of time in idle period without doing any active operation.

Energy saved from PSO should be more than the energy spent in performing PSO sequence (includes supportive Hardware mechanism). Power sequence control is done by a separate Power Controller management mechanism in hardware or can be controlled by software configuration. The sequence of operation in PSO is shown below.

Power Shut Off Sequence

The time relation between each sequence will depend on the bus frequency or the Power controller mechanism frequency. Since this PSO operation is done for Power reduction, Power management mechanism itself can run at a very low speed. The time gap between the sequence is shown as a `define parameter, so a verification engineer can change these numbers for different scenarios.

SVA should verify PSO for the below listed  points:

1. the sequence of operation

2. time relation between the control signals

3. proper power entry and exit with power thrashing conditions (energy saved < energy spent)

SVA will quickly verify PSO more efficiently during the design phase.

/*

3. UPF Strategy - Low Power ASSERTIONS for Power Sequence

- PSO Sequence

1. CG gating         - assertion (1 to 0)

2. Isolation enable  - assertion (0 to 1)

3. Retention save    - assertion (0 to 1)

4. Shut off enable   - assertion (0 to 1)

5. Shut off disable  - deassertion (1 to 0)

6. Reset activity    - application

7. Retention restore - deassertion (1 to 0)

8. Isolation disable - deassertion (1 to 0)

9. CG gating         - deassertion (0 to 1)

*/

module low_power_assertions();

reg power_controller_clk;

reg iso_ctrl;

reg ret_ctrl;

reg shut_off_ctrl;

reg rst_n;

reg clk_gate_ctrl;

`ifndef SYNTH

`define RET_START_CYCLE                    2

`define RET_DETECT_RANGE_CYCLE     5

`define SHUT_START_CYCLE      2

`define SHUT_DETECT_RANGE_CYCLE   8

`define OFF_TIME                                50

`define RST_ACTIVITY_START_CYCLE   2

`define RST_MCP                                           3

`define RET_RESTORE          2

`define ISO_DIS_DLY  2

`define CG_ENB_DLY  2

`define POWER_EXIT_TIME                     10

  `define true 1

sequence PSO_ENTRY;

 $fell(iso_ctrl) ##[`RET_START_CYCLE:`RET_DETECT_RANGE_CYCLE]                                     $fell(ret_ctrl)

 ##[`SHUT_START_CYCLE:`SHUT_DETECT_RANGE_CYCLE] $fell(shut_off_ctrl);  

endsequence

sequence PSO_EXIT;

 (##`OFF_TIME $rose(shut_off_ctrl))

 (##`POWER_EXIT_TIME `true)

 (##`RST_ACTIVITY_START_CYCLE $fell(rst_n))

 (##`RST_MCP $rose(rst_n))

 (##`RET_RESTORE $rose(ret_ctrl))

 (##`ISO_DIS_DLY $rose(iso_ctrl))

 (##`CG_ENB_DLY $rose(clk_gate_ctrl));

    endsequence

a1:assert property(@(posedge power_controller_clk) PSO_ENTRY)

$display ("PSO ENTRY SUCCESS \n");

else

$display ("PSO ENTRY FAILURE \n");

a2:assert property(@(posedge power_controller_clk) PSO_ENTRY |-> PSO_EXIT)

$display ("PSO SEQUENCE SUCCESS \n");

else

$display ("PSO SEQUENCE FAILURE \n");

c1:cover property (@(posedge power_controller_clk) PSO_ENTRY |-> PSO_EXIT);

`endif

endmodule

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