Advanced RTL Design Techniques

If you think that setup time and hold time can take negative values?  The answer is 'YES'. General Data constraint for setup time and hold time for a positive edge-triggered flop is shown in the below Figure 1. Figure 1: Setup Time and Hold Time for Positive edge-triggered flop What is negative setup time and hold time? If setup time window shifted or moves to the right side and a hold time window moves to the left side is called a negative setup time and a negative hold time. The next question immediately arises to our mind when this will happen? This can happen in a real device because of disparate internal device delays between the internal clock and data signal paths. Internal delays of a flop will arise only after the DFT insertion of Physical Design Stage. Delays added in the Flop in two ways in the: Data Path Clock Path Data Path delay is due to mux for selection between Data input and  Scan input. Clock Path delay is due to CGIC element. Figur...