Are you thinking that setup time and hold time can take negative value!!!

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If you think that setup time and hold time can take negative values? 
The answer is 'YES'.

General Data constraint for setup time and hold time for a positive edge-triggered flop is shown in the below Figure 1.
Figure 1: Setup Time and Hold Time for Positive edge-triggered flop
What is negative setup time and hold time?
If setup time window shifted or moves to the right side and a hold time window moves to the left side is called a negative setup time and a negative hold time.

The next question immediately arises to our mind when this will happen?
This can happen in a real device because of disparate internal device delays between the internal clock and data signal paths.
Internal delays of a flop will arise only after the DFT insertion of Physical Design Stage. Delays added in the Flop in two ways in the:

  1. Data Path
  2. Clock Path


Data Path delay is due to mux for selection between Data input and  Scan input.
Clock Path delay is due to CGIC element.
Figure 2: Standard cell building blocks of Flip flop
D1 - represents data path element delay
D2 - represents clock path element delay


Comparatively, if the delay of D2 is more than D1 (i.e) clock path delay is more than data path delay, this comes to a situation where setup time window seems to shift to the right side.

Figure 3: Negative Setup Time of positive edge-triggered flop
Comparatively, if the delay of D1 is more than D2 (i.e) data path delay is more than clock path delay, this comes to a situation where hold time window seems to shift to the left side.
Figure 4: Negative Hold Time of positive edge-triggered flop

Timing analysis of an ASIC design is done in two stages:

  1. STA with Synthesized netlist (with Ideal clock tree netlist)
  2. STA with Post PNR netlist (after DFT and CTS inserted netlist) 

Figure5: Library Negative Hold Time

Figure 6: Library Negative Setup Time
Figure 5 and Figure 6 is added to show that library uses negative hold time and negative setup time for post PNR STA analysis.

References:

  1. http://www.ee.bgu.ac.il/~digivlsi/slides/STA_9_1.pdf
  2. file:///D:/verilog-ieee.pdf

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