How reset synchronizer avoids metastability?

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Recovery and Removal Time. 

  • These are timing checks for asynchronous signals similar to the setup and hold check
  • Asynchronous reset also should satisfy these checks in design to avoid metastability
  • For Asynchronous reset, the problem with metastability will arise only while de-assertion of reset. Since de-assertion of reset can also be asynchronous.
  • Reset synchronizer is the best way to avoid metastability 
In the above figure, even though rst_n has been connected to both the flops. How the second flop avoids metastability?
  • The first flop input is tied to logic-1 
  • For the worst case, consider the reset is removed closest to the active edge of the clock
  • the first flop shows metastability since it has to react to two different values - for input logic-1 or for reset value logic-0
  • in the case of the second flop, the input and output of the flop is at logic level-0 while during reset removal, it avoids metastability since there is no logic level change

Comments

  1. UnknownMarch 31, 2020 at 6:42 AM

    Nice work bro!!
    Needs some clarification
    1. Meta-stability problem arises during reset assertion also right? Eventhough functional it wouldn't create any issue ( since the system is going to reset state), but in previous article, u mentioned that metastability can causes huge power drain. How this will be handled ?
    2.How basically meta-stability occurs when reset signal changes during setup and hold time of clock ?

    ReplyDelete

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