Is your design honours the chip power budget???

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Does the design honour power budget? Who will be responsible to ensure the estimated power metric aligned with chip power budget target?? 
"It is responsibility of the engineer working in every stage of ASIC development to ensure the power estimated will be within power budget of that stage of the design and keep the chip competitive in market with other vendors".
EDA vendors are having solution for a early RTL Power estimation. Some EDA tools in market are 
1. Cadence - Joules RTL Power Soution
2. Mentor Graphics - PowerPro
These above tools are pretty famous since their turn around time of report generation is very minimal when compared with formal EDA Physical design tools.
Design engineer can make use of any one of the above tool to find RTL power after a new feature or old feature enhancement or large number of bug fixes or before RTL release. Power optimization impact is more in the top level abstraction of design than in the below stages of design. 
During RTL development phase, designers first goal is to improve dynamic power reduction. The following figure 1 shows a simple example of a design TOP.v having two instance A.v, B.v and C.v. Let see how to do dynamic power analysis for the described design.
Figure 1: Top.v RTL Power Report
Figure 2: Top.v CGIC Power Report
CG - Clock Gating
CG ratio - Percentage of gated flops in a design
CG efficiency - Percentage of flops is being gated for the switching activity
In order to do proper dynamic power analysis, the dynamic power test case database needs to be perfect, why because since tool will generate CG efficiency based on the switching activity database.
Points to Analyse:
  1. Module B is having CG ratio of 85% and CG efficiency of 90%, this is not the correct module for dynamic power optimization
  2. Module A and C are having CG ratio of 80% and 90% with CG efficiency of 55% and 45% percentage which clearly tells that the CG enables for the modules in A and C are not efficiently gating the flops in A and C. So, further RTL review for the correct enables needs to be identified for the design A and C.
  3. From Figure 2, Clock gating efficiency of ICG1, ICG2 and ICG3 are 50%, 80% and 85% respectively. ICG1 CG efficiency is very critical for Dynamic power optimization. So for first cut of optimization, designer should concentrate on weak efficient CGIC with more dynamic power dissipation network.
RTL is updated as a part of the above analysis and again the tool is triggered to analyze the optimization effect on RTL by analysing Power report.

References:
  1. IP Power Analysis Semiconductor Engineering https://www.youtube.com/watch?v=czK60j65JLo
  2. ARM uses Mentor's PowerPro tool to achieve power budget of their design IP https://semiwiki.com/semiconductor-ip/arm/6423-how-arm-designs-and-optimizes-socs-for-low-power/

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