Introduction to AXI

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 Key concepts on how to implement the AXI protocol In older ARM documentation , 

Master and Slave termininology is mentioned.
 Now its been changed to Manager and Subordinate. 

Advanced Microcontroller Bus Architecture => On chip interconnect specification Benefits of AMBA: 
1. IP reuse & Flexibility - Standard interface enables IP reuse across products 
2. Compatability - Standard interface helps us in working with different IP vendors 

Metrics : 
1. Bandwidth 
2. Latency
AXI is a point to point specification so only interface level info and timing info are concentrated. In order for Multi Manager and Multi Subordinate to be connected. Bus interconnect is required.
  • AXI has 3 channel for write interface and 2 channel for read interface like in above figure.
  •  Why Wr channel has separate response ?
    • Response is required by master which slave acknowledge the transfer is valid for that slave or not . also AW, W are directional from master to slave. Response is required from slave to master. So separate channel is required for write response 
  • Why Write response is having a B prefix in it ?
    •  After write transcation is completed, the slave will initiate the response. So Write response is buffered. Thats why write response B prefix is used.
  •  What are the main axi feature ? 
    • Independent rd and wr channel increases performance in full duplex
    •  multiple outstanding address 3.
    •  all channel are independent - no timing relationship between channels
    •  out of order transaction completion are supported based on ID support. Increase performance.
    • Support of unaligned data transfer -minimum unit is byte addressable. Not aligned to 32 bit boundary. can also support 0x1,0x2,... Generally master can give 32 bit boundary aligned address and can handle in wr strobe interms of write transaction. In terms of read, the data which got read other than expected address location can be discarded*. *Data sensistive element like FIFO cannot be handled like this for read transaction. 
    •  burst transaction based on start address, only start address can alone be shared, slave will take care of the address computation. So power on address computation and related data toggling power are saved in master and interconnect side

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