Essential Memory Criteria for Trending Technology nodes

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Static Random Access Memory is a very basic entity in all System on Chip. For every advancement of technology node, there will be a further increase in the leakage power when compared with previous nodes.
A designer should choose a memory vendor who should support low power mode for on-chip SRAM (Macro). By using this, the designer can compile their respective memory size which adopts some kind of mechanisms to place the memory under power efficient modes.
Single Port Memory Macro
The above figure shows a single port SRAM Macro. ME-Memory Enable, WE-Write Enable, CLK-clock, Addr-Address, Datain are the Inputs. Dataout bus is the Output.
Memory Operation-Write/Read
The internal blocks of a simple SRAM are : 
1. Peripheral blocks 
2. Memory array 
Peripheral blocks include Input and Output IO buffer, Row and Column decoder, Sense circuits, Data output register. 
The below figure gives the idea about the internal block diagram of Synchronous simple SRAM.
Synchronous SRAM
So in a typical SRAM, the internal blocks consist of peripheral logic and memory array is shown in the below figure. Blocks with orange background depict peripheral logic and green background represents memory array.
Internal Structure of SRAM
Power dissipation in memory macros are :
1. Dynamic Power - This will happen whenever there is a transition at the memory inputs 
2. Leakage Power - This will depend on the state of the memory inputs. So, wherever possible we should cut down the leakage power by adopting low power modes

Depends on the memory usage and after an end of a transaction, the memory can be subjected to under any one of the low power modes. They are :
1. Light Sleep
  • In Light Sleep all peripheral logics are shut-down and isolated this saves leakage power in periphery circuits of around 30% - 40%
  • Data in the memory is retained after exiting from the light sleep
  • The memory will take a little amount of time to exit from Light sleep
2. Deep Sleep 
  • In Deep Sleep mode both peripheral logic and memory array are under shutdown and this gives a savings of around 80%-95%
  • The memory will take some amount of time to exit from a deep sleep
  • Data in the memory is not retained after exiting from the deep sleep
  • The exit time from Deep sleep will be more than light sleep since the majority of logic are going under shutdown
The Pictorial representation of SRAM after Light sleep and Deep sleep implementation is shown below.
SRAM MACRO WITH LOW POWER FEATURES
  • Power Switch fabric needs to be inserted to switch off 
    • periphery logic during light sleep
    • both periphery logic and memory array during deep sleep
  • Isolation cells need to be inserted 
    • To protect memory contents during light sleep, since memory array is ON so there is a need for isolation between peripheral logic and memory array
    • To prevent output peripheral logic from sending floating values to higher hierarchies in design
Impacts of Sleep Logic:
  • The memory will take some time to enter and to exit from sleep, this should be considered for achieving design metrics 
  • Two separate control signals are needed for achieving fine level low power modes (light sleep, deep sleep)
Conclusion:
The designer should prefer a memory vendor who should have a provision of generating low power modes for their memories.

References:
[2] An ASIC Low Power Primer by J.Bhaskar

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