Advanced RTL Design Techniques

Static Random Access Memory is a very basic entity in all System on Chip. For every advancement of technology node, there will be a further increase in the leakage power when compared with previous nodes. A designer should choose a memory vendor who should support low power mode for on-chip SRAM (Macro). By using this, the designer can compile their respective memory size which adopts some kind of mechanisms to place the memory under power efficient modes. Single Port Memory Macro The above figure shows a single port SRAM Macro. ME-Memory Enable, WE-Write Enable, CLK-clock, Addr-Address, Datain are the Inputs. Dataout bus is the Output. Memory Operation-Write/Read The internal blocks of a simple SRAM are :  1. Peripheral blocks  2. Memory array  Peripheral blocks include Input and Output IO buffer, Row and Column decoder, Sense circuits, Data output register.  The below figure gives the idea about the internal block diagram of Synchronous simple SRAM. S

Power Shut OFF is a low power strategy which cuts off leakage current over a period of time. PSO intent is captured and intimated to the Design compiler tool using Unified Power Format File (UPF) . UPF file captures the power intent of the RTL in a separate format. https://www.google.com/url?sa=t&source=web&rct=j&url=http://citeseerx.ist.psu.edu/viewdoc/download%3Fdoi%3D10.1.1.133.6194%26rep%3Drep1%26type%3Dpdf&ved=2ahUKEwjNlej5qNXiAhUIU30KHVoHDS0QFjAAegQIBBAB&usg=AOvVaw0soeOeXE2zTfuZHKVmCXus PSO implementation includes the following strategy that are attached to the design in the later implementation phases : 1. Creation of Power Domain (PD) 2. Isolation Strategy 3. Retention Strategy 4. Power switch Let us dive further into this topic with a simple example.  Consider a Design unit as shown in the figure. This system consists of a simple Design top with Block A as shown below. RTL DESIGN TOP  Let us start building a UPF for this DESI

LOW POWER DESIGN - SYSTEM VERILOG ASSERTIONS (SVA) Power Gating has become the most common strategy in today's trending nm technology. Power intent designs are dominating the chip, which needs more verification attention and different strategies to verify the intents. So, a generic SVA is arrived to verify the Power Shut Off (PSO) sequence. A major decision to make is choosing which design should adopt PSO. PSO is most favourable for a design which spends an accountable amount of time in idle period without doing any active operation. Energy saved from PSO should be more than the energy spent in performing PSO sequence (includes supportive Hardware mechanism). Power sequence control is done by a separate Power Controller management mechanism in hardware or can be controlled by software configuration. The sequence of operation in PSO is shown below. Power Shut Off Sequence The time relation between each sequence will depend on the bus frequency or the Powe