Advanced RTL Design Techniques

  RTL Requirements : 1. Data width = 32 or 64 bits  (Downsizer may required based on master interface this slave is getting connected with) 2. Burst length supported = 1   ( AxBURST = 0x1 ) 3. Memory type = non-bufferable, non-modifiable (AxCACHE [3:0] = 0x0) 4. Write Strobe = supported 5. Outstanding transaction = Optional to slave Most slave dont support outstanding transaction 6. ID support : Simply slave should reply with ID it been received 7. xLAST = considered as 0x1 for read and write transfer 8. AxLOCK, AxCACHE, AxPROT = 0x0 not supported 9. xRESP - EXOKAY not supported

  Key concepts on how to implement the AXI protocol In older ARM documentation ,  Master and Slave termininology is mentioned.  Now its been changed to Manager and Subordinate.  Advanced Microcontroller Bus Architecture => On chip interconnect specification Benefits of AMBA:  1. IP reuse & Flexibility - Standard interface enables IP reuse across products  2. Compatability - Standard interface helps us in working with different IP vendors  Metrics :  1. Bandwidth  2. Latency AXI is a point to point specification so only interface level info and timing info are concentrated. In order for Multi Manager and Multi Subordinate to be connected. Bus interconnect is required. AXI has 3 channel for write interface and 2 channel for read interface like in above figure.  Why Wr channel has separate response ? Response is required by master which slave acknowledge the transfer is valid for that slave or not . also AW, W are directional from master to slave. Response is required from slave to

Active transaction or Outstanding transaction for AXI  Definition of outstanding transaction on Read Channel : Read address is placed and waiting for the read data. Number of such AR transaction accepted between read address and last read data for the particular read address is simply the number of outstanding transaction on read channel Definition of outstanding transaction on Write Channel : For write transactions, the data can come after the address, but leading write data is also allowed. The start of a write transaction can therefore be either of the following: • The transfer of the write address • The transfer of leading write information Therefore, an active write transaction is a transaction for which the write address or leading write data has been transferred, but the write response has not yet been transferred. Simply we can say the number of transaction accepted on AW channel between first AW and the Bresp on the write channel will give outstanding transaction on write

First let us discuss the need for Asynchronous FIFO. We use Gray code for the same reason we need Async FIFO. To transfer a stream of multi bit signal(bus) from one clock domain to a different clock domain, designers cannot use typical Data Synchronizers. Different bus signals from different data synchronizers converge at different period of time, and this typical problem is called the Re-convergence issue in ASIC Design world. To solve the problem, Asynchronous FIFO was designed. Again in Asynchronous FIFO, pointers should be synchronized from native clock domain to the other clock domain. Pointers are multi bit which could lead to re convergence issue all over again. Luckily, we know that pointers are not random unlike data stream. Both Read and Write pointers are incremented by one (+1) w.r.t clock edge on read & write from FIFO. Given that, we should look for a code which changes minimally on increment by one (ideally only one bit change), Gray code was the solution. Employing

1. Clock gating will impact in reducing 1. clock network power 2. leakage power 3. static power  2. Effect of CG insertion may cause   1. setup time violation   2. hold time violation   3. both   3. Pick the correct latch combination within a CG element of posedge and negedge trigger flops   1. active low latch, active low latch   2. active low latch, active high latch   3. active high latch, active low latch  4. Can we directly use a signal from a different clock domain as enable to CG element   1. Yes   2. No  5. Gated clock generated by CG element is    1. synchronous with respect to the input clock   2. asynchronous with respect to the input clock