Advanced RTL Design Techniques

Rule of Seven: Human mind can hold up to seven objects in one time Applying this rule in Chip design: FSM state which crossed 7 (or up to 9) states can be changed to HFSM- Hierarchical FSM which helps designers and architects easy to think, review, debug In SoC, If we have more than 7 (or up to 9) blocks under one hierarchy which indicates the structure is getting more complex. So design partition needed to minimize complexity Psychologically mind looks for more opportunities when we feed it with minimal objects. So at one time, we need to see minimal design objects for efficient thinking & design. Reference: Simple Art of SoC Design

APB Change Points

Recovery and Removal Time .  These are timing checks for asynchronous signals similar to the setup and hold check Asynchronous reset also should satisfy these checks in design to avoid metastability For Asynchronous reset, the problem with metastability will arise only while de-assertion of reset. Since de-assertion of reset can also be asynchronous. Reset synchronizer is the best way to avoid metastability  In the above figure, even though rst_n has been connected to both the flops. How the second flop avoids metastability? The first flop input is tied to logic-1  For the worst case, consider the reset is removed closest to the active edge of the clock the first flop shows metastability since it has to react to two different values - for input logic-1 or for reset value logic-0 in the case of the second flop, the input and output of the flop is at logic level-0 while during reset removal, it avoids metastability since there is no logic level change ...