Basic of Clock Gating
1. Clock gating will impact in reducing 1. clock network power 2. leakage power 3. static power 2. Effect of CG insertion may cause 1. setup time violation 2. hold time violation 3. both 3. Pick the correct latch combination within a CG element of posedge and negedge trigger flops 1. active low latch, active low latch 2. active low latch, active high latch 3. active high latch, active low latch 4. Can we directly use a signal from a different clock domain as enable to CG element 1. Yes 2. No 5. Gated clock generated by CG element is 1. synchronous with respect to the input clock 2. asynchronous with respect to the input clock